Xilinx Unveils the Vivado Design Suite for the Next Decade of 'All Programmable' Devices
IP and system-centric tool suite built from the ground up to accelerate programmable systems integration and implementation by up to 4X
San Jose, California, April 24, 2012 /PRNewswire via COMTEX/ - Xilinx, Inc. (NASDAQ: XLNX) today announced the Vivado(TM) Design Suite, a new IP and system-centric design environment built from the ground up to accelerate design productivity for the next decade of 'All Programmable' Devices. Vivado tools not only speed the design of programmable logic and I/O, but accelerate programmable systems integration and implementation into devices incorporating 3D stacked silicon interconnect technology, ARM® processing systems, Analog Mixed Signal (AMS), and a significant percentage of semiconductor intellectual property (IP) cores. With up to a 4X productivity advantage over competing development environments, the Vivado Design Suite attacks the major bottlenecks in programmable systems integration and implementation.
"Vivado tools are the culmination of work started by Xilinx engineers in 2008 in response to customers' needs for more productivity, faster time to market, and the ability to go beyond programmable logic to programmable systems integration. It has been beta tested with more than 100 customers and Alliance Program members over the past 12 months, including customers using our stacked siliconfor extreme capacity and bandwidth," said Xilinx senior vice president of platforms development, Victor Peng.
Vivado Design Environment
The Vivado Design Suite provides a highly integrated design environment (IDE) with a completely new generation of system-to-IC level tools, all built on the backbone of a shared scalable data model and a common debug environment. It is also an open environment based on industry standards such as the AMBA4 AXI4 interconnect specification, IP-XACT IP packaging metadata, the Tool Command Language (Tcl), Synopsys Design Constraints (SDC) and others that facilitate design flows tailored to the user's needs. Xilinx architected Vivado tools to enable the combination of all types of programmable technologies and scale up to 100-million-ASIC equivalent gate designs.
To address integration bottlenecks, the Vivado IDE includes electronic system level (ESL) design tools for rapidly synthesizing and verifying C-based algorithmic IP; standards based packaging of both algorithmic and RTL IP for reuse; standards based IP stitching and systems integration of all types of system building blocks; and the verification of blocks and systems with 3X faster simulation, while hardware co-simulation provides 100X more performance.
To address implementation bottlenecks, Vivado tools include a hierarchical device editor and floor planner, a 3-15X faster logic synthesis tool with industry leading support for SystemVerilog, and a 4X faster, more deterministic place and route engine that uses analytics to minimize a 'cost' function of multiple variables such as timing, wire length and routing congestion. In addition, incremental flows allow for engineering change order (ECO) induced changes to be quickly processed by only re-implementing a small part of the design, while preserving performance. Finally, leveraging the new shared scalable data model, the tools provide power, timing and area estimates at every stage of the design flow, enabling up front analysis and then optimization with integrated capabilities such as automated clock gating.
"The combination of the Vivado Design Suite and the Virtex-7 2000T FPGA has created a paradigm shift in the programmable logic industry. Vivado has enabled Broadcom to design with the industry's highest capacity FPGA without any manual floorplanning or partitioning," said Paul Rolfe, manager, hardware development engineering, Broadcom Europe. "We are impressed with the innovation that Xilinx is delivering both in silicon and software."
The version 2012.1 is available as part of an early access program. Customers should contact their local Xilinx representative. Public access will commence with version 2012.2 early this summer, followed by WebPACK(TM) availability and extensible processing platform (EPP) support later in the year. ISE® Design Suite Edition customers with current support will be provided the new Vivado Design Suite Editions in addition to ISE at no additional cost. The will continue to be supported by Xilinx for customers targeting 7 series devices and prior generations. To learn more, please visit .
Xilinx develops All Programmable technologies and devices, beyond hardware to software, digital to analog, and single to multiple die in 3D ICs. These industry leading devices are coupled with a next-generation design environment and IP to serve a broad range of customer needs, from programmable logic to programmable systems integration. For more information, visit .
Xilinx Unveils the Vivado Design Suite
April 24, 2012
Since Xilinx began working on the Vivado Design Suite four years ago, it has engaged with hundreds of Xilinx Alliance Program members and customers to bring the tools to a mature state for release. Each has played a role in helping to ensure that Xilinx has built a highly productive set of tools for breaking through integration and implementation bottlenecks as customers design their next generation 'All-Programmable' devices. Here's what some of them have to say about the Vivado Design Suite.
"As a Premier Design Services member of the Xilinx Alliance Program, Fidus has developed many leading-edge Xilinx-based products for technology companies across North America. The Vivado Design Suite's superior user interface and support for ASIC design industry standards such as System Verilog, SystemC, SDC and Tcl will greatly accelerate our design productivity. Xilinx's Vivado Design Suite sets a new industry benchmark and further enables Fidus to deliver complex, high quality, leading edge Xilinx designs to our clients."
-, Vice President, Engineering
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